CY28442-2
....................... Document #: 38-07691 Rev. *B Page 6 of 19
Byte 3: Control Register 3
Bit
@Pup
Name
Description
7
0
SRC7
Allow control of SRC[T/C]7 with assertion of PCI_STP# or SW PCI_STP#
0 = Free running, 1 = Stopped with PCI_STP#
6
0
SRC6
Allow control of SRC[T/C]6 with assertion of PCI_STP# or SW PCI_STP#
0 = Free running, 1 = Stopped with PCI_STP#
5
0
SRC5
Allow control of SRC[T/C]5 with assertion of PCI_STP# or SW PCI_STP#
0 = Free running, 1 = Stopped with PCI_STP#
4
0
SRC4
Allow control of SRC[T/C]4 with assertion of PCI_STP# or SW PCI_STP#
0 = Free running, 1 = Stopped with PCI_STP#
3
0
SRC3
Allow control of SRC[T/C]3 with assertion of PCI_STP# or SW PCI_STP#
0 = Free running, 1 = Stopped with PCI_STP#
2
0
SRC2
Allow control of SRC[T/C]2 with assertion of PCI_STP# or SW PCI_STP#
0 = Free running, 1 = Stopped with PCI_STP#
1
0
SRC1
Allow control of SRC[T/C]1 with assertion of PCI_STP# or SW PCI_STP#
0 = Free running, 1 = Stopped with PCI_STP#
0
RESERVED
Byte 4: Control Register 4
Bit
@Pup
Name
Description
7
0
96_100_SSC
96_100_SSC Drive Mode
0 = Driven in PWRDWN, 1 = Tri-state
6
0
DOT96T/C
DOT_PWRDWN Drive Mode
0 = Driven in PWRDWN, 1 = Tri-state
5
0
RESERVED
4
0
PCIF1
Allow control of PCIF1 with assertion of SW and HW PCI_STP#
0 = Free running, 1 = Stopped with PCI_STP#
3
0
PCIF0
Allow control of PCIF0 with assertion of SW and HW PCI_STP#
0 = Free running, 1 = Stopped with PCI_STP#
2
1
CPU[T/C]2
Allow control of CPU[T/C]2 with assertion of CPU_STP#
0 = Free running, 1 = Stopped with CPU_STP#
1
CPU[T/C]1
Allow control of CPU[T/C]1 with assertion of CPU_STP#
0 = Free running, 1 = Stopped with CPU_STP#
0
1
CPU[T/C]0
Allow control of CPU[T/C]0 with assertion of CPU_STP#
0 = Free running, 1 = Stopped with CPU_STP#
Byte 5: Control Register 5
Bit
@Pup
Name
Description
7
0
SRC[T/C]
SRC[T/C] Stop Drive Mode
0 = Driven when PCI_STP# asserted,1 = Tri-state when PCI_STP#
asserted
6
0
CPU[T/C]2
CPU[T/C]2 Stop Drive Mode
0 = Driven when CPU_STP# asserted,1 = Tri-state when CPU_STP#
asserted
5
0
CPU[T/C]1
CPU[T/C]1 Stop Drive Mode
0 = Driven when CPU_STP# asserted,1 = Tri-state when CPU_STP#
asserted
4
0
CPU[T/C]0
CPU[T/C]0 Stop Drive Mode
0 = Driven when CPU_STP# asserted,1 = Tri-state when CPU_STP#
asserted
3
0
SRC[T/C][7:1]
SRC[T/C] PWRDWN Drive Mode
0 = Driven when PD asserted,1 = Tri-state when PD asserted
2
0
CPU[T/C]2
CPU[T/C]2 PWRDWN Drive Mode
0 = Driven when PD asserted,1 = Tri-state when PD asserted
1
0
CPU[T/C]1
CPU[T/C]1 PWRDWN Drive Mode
0 = Driven when PD asserted,1 = Tri-state when PD asserted
相关PDF资料
CY28445LFXC-5 IC CLOCK CALISTOGA CK410M 68QFN
CY28446LFXC IC CLOCK CALISTOGA CK410M 64QFN
CY28447LFXC IC CLOCK CALISTOGA CK410M 72QFN
CY28547LFXCT IC CLOCK CK505/410M INTEL 72QFN
CY28548ZXC IC CLK CK505 960M/965M 64TSSOP
CY28551LFXC-3T IC CLOCK INTEL/AMD SIS VIA 56QFN
CY28551LFXC IC CLOCK INTEL/AMD SIS VIA 64QFN
CY2SSTV855ZXI IC CLOCK DIFFDRV PLL DDR 28TSSOP
相关代理商/技术参数
CY28442ZXC-2T 功能描述:时钟发生器及支持产品 Calistoga RoHS:否 制造商:Silicon Labs 类型:Clock Generators 最大输入频率:14.318 MHz 最大输出频率:166 MHz 输出端数量:16 占空比 - 最大:55 % 工作电源电压:3.3 V 工作电源电流:1 mA 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:QFN-56
CY28442ZXCT 功能描述:IC CLOCK GEN ALVISO 56-TSSOP RoHS:是 类别:集成电路 (IC) >> 时钟/计时 - 时钟发生器,PLL,频率合成器 系列:- 产品变化通告:Product Discontinuation 04/May/2011 标准包装:96 系列:- 类型:时钟倍频器,零延迟缓冲器 PLL:带旁路 输入:LVTTL 输出:LVTTL 电路数:1 比率 - 输入:输出:1:8 差分 - 输入:输出:无/无 频率 - 最大:133.3MHz 除法器/乘法器:是/无 电源电压:3 V ~ 3.6 V 工作温度:0°C ~ 70°C 安装类型:表面贴装 封装/外壳:16-TSSOP(0.173",4.40mm 宽) 供应商设备封装:16-TSSOP 包装:管件 其它名称:23S08-5HPGG
CY28443 制造商:CYPRESS 制造商全称:Cypress Semiconductor 功能描述:Clock Generator for Intel㈢ Calistoga Chipset
CY28443-2 制造商:CYPRESS 制造商全称:Cypress Semiconductor 功能描述:Clock Generator for Intel㈢ Calistoga Chipset
CY28443-3 制造商:SPECTRALINEAR 制造商全称:SPECTRALINEAR 功能描述:Clock Generator for Intel㈢ Calistoga Chipset
CY28443OXC 制造商:CYPRESS 制造商全称:Cypress Semiconductor 功能描述:Clock Generator for Intel㈢ Calistoga Chipset
CY28443OXC-2 制造商:CYPRESS 制造商全称:Cypress Semiconductor 功能描述:Clock Generator for Intel㈢ Calistoga Chipset
CY28443OXC-2T 制造商:CYPRESS 制造商全称:Cypress Semiconductor 功能描述:Clock Generator for Intel㈢ Calistoga Chipset